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Application Information
Regulator
Current Multiplier
V?I Chip Regulator
V F =
0.01 μ F
10 k Ω
VC
PC
TM
IL
NC
PR
PRM?-AL
+In +Out
VH
SC
SG
OS
NC
CD
R OS
R CD
V L
K
0.4 μH
+
(I L ? Ro)
K
+In
TM
VC
PC
+Out
+Out
VTM?
– Out
L
O
A
V IN
–In
–Out
10 Ω
– In
K
Ro
– Out
D
Figure 16 — Adaptive Loop compensation with soft start using the SC port.
Output Voltage Setting with Adaptive Loop
The equations for calculating R OS and R CD to set a VTM output
voltage are:
Output Voltage Trimming (optional)
After setting the output voltage from the procedure above the output
may be margined down (26 Vf min) by a resistor from SC-SG using this
formula:
93100
R OS =
( V L ? 0.8395 ) – 1
(1)
R d Ω =
10000 V fd
K
V fs - V fd
R CD =
91238
R OS
+1
(2)
Where V fd is the desired factorized bus and V fs is the set factorized bus.
A low voltage source can be applied to the SC port to margin the load
voltage in proportion to the SC reference voltage.
An external capacitor can be added to the SC port as shown in Figure 16
V L = Desired load voltage
V OUT = VTM output voltage
K = VTM transformation ratio
to control the output voltage slew rate for soft start.
(available from appropriate VTM data sheet)
V f = PRM output voltage, the Factorized Bus (see Figure 16)
R O = VTM output resistance
(available from appropriate VTM data sheet)
I L = Load Current
(actual current delivered to the load)
Nominal Vout
Range (Vdc)
0.8 ? 1.6
1.1 ? 2.2
1.6 ? 3.3
2.2 ? 4.4
3.3 ? 6.6
VTM
K Factor
1/32
1/24
1/16
1/12
1/8
4.3 ?
6.5 ?
8.7 ?
13.0 ?
17.4 ?
26.0 ?
8.8
13.4
17.9
26.9
36.0
54.0
1/6
1/4
1/3
1/2
2/3
1
Table 2 — 048 input series VTM K factor selection guide
vicorpower.com
800-735-6200
V?I Chip Regulator
P036F048T12AL
Rev. 1.9
Page 9 of 14
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